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Disambiguation of "Tsiokanos, Ioannis"

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Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning.

, , , and . IEEE Des. Test, 40 (1): 34-42 (February 2023)

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Ioannis Gavriel

Ioannis Filippis

Ioannis Tzamichas

Ioannis Efthimiadis

Ioannis Vardoulakis

 

Other publications of authors with the same name

ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis., , , , and . IEEE Trans. Computers, 72 (4): 1026-1040 (April 2023)Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations., , , , and . ICCD, page 455-462. IEEE, (2022)Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation., , , , and . ISQED, page 225-230. IEEE, (2020)DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search., , , , and . DATE, page 1121-1126. IEEE, (2020)Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit., , , and . ISLPED, page 52:1-52:6. ACM, (2018)Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation., , , and . IOLTS, page 171-176. IEEE, (2018)DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices., , , , and . ACM J. Emerg. Technol. Comput. Syst., 17 (3): 32:1-32:24 (2021)Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation., , and . DATE, page 698-703. IEEE, (2019)ExHero: Execution History-Aware Error-Rate Estimation in Pipelined Designs., and . IEEE Micro, 41 (1): 61-68 (2021)Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning., , , and . IEEE Des. Test, 40 (1): 34-42 (February 2023)