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Maze routing with buffer insertion and wiresizing.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1205-1209 (2002)

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Maze routing with buffer insertion and wiresizing., and . DAC, page 374-378. ACM, (2000)Maze routing with buffer insertion and wiresizing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1205-1209 (2002)Maze routing with buffer insertion under transition time constraints., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (1): 91-95 (2003)Floorplanning with power supply noise avoidance., , , , and . ASP-DAC, page 427-430. ACM, (2003)Maze Routing with Buffer Insertion under Transition Time Constraints., , , and . DATE, page 702-707. IEEE Computer Society, (2002)Memory-efficient interconnect optimization., and . ASP-DAC, page 198-202. ACM, (2001)Slicing tree is a complete floorplan representation., and . DATE, page 228-232. IEEE Computer Society, (2001)