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Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor., , , , , , , and . A-SSCC, page 373-376. IEEE, (2014)Parallel Algorithms for VHDL Simulation. University of Illinois Urbana-Champaign, USA, (1997)Implications of VHDL timing models on simulation and software synthesis., , and . J. Syst. Archit., 44 (1): 23-36 (1997)System Modeling, Performance Analysis, and Evolutionary Prototyping with Hardware Description Languages., , and . MASCOTS, page 312-318. IEEE Computer Society, (1995)Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors., , , , , , and . International Conference on Supercomputing, page 172-179. ACM, (1997)A switch level fault simulation environment., , and . DAC, page 780-785. ACM, (2000)WADE: a Web-based automated parallel CAD environment., , , , , and . HiPC, page 473-480. IEEE Computer Society, (1998)graze: A Tool for Performance Visualization and Analysis., , , , , , and . ICPP (2), page 135-138. CRC Press, (1995)Automatic Parallelization of Compiled Event Driven VHDL Simulation., , and . IEEE Trans. Computers, 51 (4): 380-394 (2002)Load Balancing and Workload Minimization Of Overlapping Parallel Tasks., , and . ICPP, page 272-279. IEEE Computer Society, (1997)