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Disambiguation of "Karnik, Tanay"

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F5: Frequency generation and clock distribution.

, , , , , , , and . ISSCC, page 508-509. IEEE, (2013)

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Izzet Tanay

Emre Tanay

Kevser Eda Tanay

 

Other publications of authors with the same name

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters., , , , , , and . IEEE J. Solid State Circuits, 42 (1): 66-73 (2007)Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors., , , , , , , and . DAC, page 486-491. ACM, (2002)High-voltage power delivery through charge recycling., , , and . IEEE J. Solid State Circuits, 41 (6): 1400-1410 (2006)Accurate Estimation of SRAM Dynamic Stability., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (12): 1639-1647 (2008)Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration.. ISPD, page 95. ACM, (2022)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies., , and . VLSI Design, page 5-7. IEEE Computer Society, (2006)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation., , , , , , , , , and . ISQED, page 547-552. IEEE, (2021)An empirical model for accurate estimation of routing delay in FPGAs., and . ICCAD, page 328-331. IEEE Computer Society / ACM, (1995)