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Disambiguation of "Nani, Claudio"

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Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications.

, , , , and . DATE, page 1390-1393. ACM, (2008)

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Nani Osada

Nani Hendiarti

Riccardo Nanini

Nani Gopal Ghoshal

Claudio Puschel

 

Other publications of authors with the same name

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET., , , , , , , , , and 15 other author(s). ISSCC, page 116-118. IEEE, (2019)A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist., , , , and . ISSCC, page 180-182. IEEE, (2011)18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET., , , , , , , , , and 16 other author(s). ISSCC, page 344-346. IEEE, (2024)A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC., , , and . ISCAS, page 1-5. IEEE, (2021)Delay-lines jitter modeling and efficiency analysis in FinFET technology., , , and . ICECS, page 1-5. IEEE, (2021)18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm., , , , , , , , , and 18 other author(s). ISSCC, page 342-344. IEEE, (2024)27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS., , , and . ISSCC, page 470-472. IEEE, (2016)Analysis and Design of a Low Power Double Tail Comparator with Dynamic Bias in 5nm FinFET Technology., , , and . PRIME, page 29-32. IEEE, (2023)A 0.94 V Dynamic Bias Double Tail Comparator for High-Speed Applications in 5 nm Technology., , , and . ApplePies, volume 1110 of Lecture Notes in Electrical Engineering, page 68-73. Springer, (2023)