A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch.
J. Kim, Y. Oh, H. Kim, J. Lee, and J. Kim. IEEE Trans. Circuits Syst. II Express Briefs, 70 (9):
3228-3232(September 2023)
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