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A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.

, , , and . FPT, page 361-364. IEEE, (2006)

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Chip size estimation based on wiring area., , , and . APCCAS (2), page 113-118. IEEE, (2002)Optimal single hop multiple bus networks., , and . ISCAS, page 2541-2544. IEEE, (1993)Minimal acyclic forbidden minors for the family of graphs with bounded path-width., , and . Discret. Math., 127 (1-3): 293-304 (1994)An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost., , , and . ASP-DAC, page 338-341. ACM, (2003)An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (3): 655-663 (2002)Mixed-Searching and Proper-Path-Width., , and . ISA, volume 557 of Lecture Notes in Computer Science, page 61-71. Springer, (1991)Partition, Packing and Clock Distribution-A New Paradigm of Physical Design., , , and . VLSI Design, page 11. IEEE Computer Society, (2000)Rectangle-packing-based module placement., , , and . ICCAD, page 472-479. IEEE Computer Society / ACM, (1995)Channel-driven global routing with consistent placement (extended abstract)., and . ICCAD, page 350-355. IEEE Computer Society / ACM, (1994)A device-level placement with multi-directional convex clustering., , , and . ACM Great Lakes Symposium on VLSI, page 196-201. ACM, (2004)