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Disambiguation of "Ryynänen, Jussi"

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Tri-Phasing Modulation for Efficient and Wideband Radio Transmitters.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 3085-3098 (2018)

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Jussi Pekonen

Jussi Kumpula

Jussi Grießinger

Narendra Jussien

Jussi Baade

 

Other publications of authors with the same name

A charge limiting and redistribution method for delay line locking in multi-output clock generation., , and . ISCAS, page 1-4. IEEE, (2017)A programmable DSP front-end for all-digital 4G transmitters., , , , , , , and . NEWCAS, page 1-4. IEEE, (2013)RX-Band Noise Reduction in All-Digital Transmitters With Configurable Spectral Shaping of Quantization and Mismatch Errors., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (11): 3256-3265 (2014)A High-Speed DSP Engine for First-Order Hold Digital Phase Modulation in 28-nm CMOS., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (12): 1959-1963 (2018)A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 50 (3): 644-655 (2015)WCDMA multicarrier receiver for base-station applications., , , , , , , and . IEEE J. Solid State Circuits, 41 (7): 1542-1550 (2006)2.4-GHz receiver for sensor applications., , , , , , and . IEEE J. Solid State Circuits, 40 (7): 1426-1433 (2005)Active polyphase filter analysis., , and . ISCAS, page 1125-1128. IEEE, (2010)A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver., , , , and . ISSCC, page 122-591. IEEE, (2007)A 1.2 - 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS., , , and . ISCAS, page 506-509. IEEE, (2014)