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An accuration delay modeling technique for switch-level timing verification.

, , and . DAC, page 227-233. IEEE Computer Society Press, (1986)

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Highlights of VLSI Research at Berkeley., , and . FJCC, page 894-897. IEEE Computer Society, (1986)WELD - An Environment for Web-based Electronic Design., , and . DAC, page 146-151. ACM Press, (1998)On the Verification of Sequential Machines at Differing Levels of Abstraction., , and . DAC, page 271-276. IEEE Computer Society Press / ACM, (1987)Experiments on the synthesis and testability of non-scan finite state machines., , and . EURO-DAC, page 537-542. IEEE Computer Society Press, (1992)Decomposition and factorization of sequential finite state machines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (11): 1206-1217 (1989)A synthesis and optimization procedure for fully and easily testable sequential machines., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (10): 1100-1107 (1989)System-level design: orthogonalization of concerns andplatform-based design., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (12): 1523-1543 (2000)Critic: a knowledge-based program for critiquing circuit designs., and . ICCD, page 324-327. IEEE, (1988)From ASIC to ASIP: The Next Design Discontinuity., , and . ICCD, page 84-90. IEEE Computer Society, (2002)Digital Image Restoration by Exposure-Splitting and Registration., , and . ICPR (4), page 657-660. IEEE Computer Society, (2004)