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Disambiguation of "Singh, Jawar"

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An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications.

, , , and . Circuits Syst. Signal Process., 42 (5): 2828-2851 (May 2023)

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Jawar Singh

Jawar Dshafarowa-Plavius

Vikramaditya Singh

Sohan Singh

Arunoday Singh

 

Other publications of authors with the same name

Performance Enhancement of Dopingless Tunnel-FET Based on Ge-Source with High-k., and . iNIS, page 19-22. IEEE, (2015)Memristor Crossbar-Based Pattern Recognition Circuit Using Perceptron Learning Rule., and . iNIS, page 236-239. IEEE, (2016)An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications., , , and . Circuits Syst. Signal Process., 42 (5): 2828-2851 (May 2023)Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications., , and . IEEE Access, (2019)Improvement in Retention Time of Capacitorless DRAM with Access Transistor., and . CoRR, (2019)Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison., , , , and . IEEE Access, (2023)A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact., and . VLSI-SoC, page 1-6. IEEE, (2023)Extended Base Schottky-Collector Bipolar Charge Plasma Transistor., and . iNIS, page 137-140. IEEE, (2015)Secure Multi-key Generation Using Ring Oscillator Based Physical Unclonable Function., , , and . iNIS, page 200-205. IEEE, (2016)Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free Transistors., , , and . iNIS, page 194-199. IEEE, (2016)