( en | de | ru )

 

Disambiguation of "Hermanek, Antonin"

Author of the publication

copydeleteadd this publication to your clipboard
Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm.

, , , and . VLSI Signal Processing, 46 (1): 35-53 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Peter Hermanek

Peter Hermanek

Peter Hermanek

Antonin Eigel

Antonin Sztraka

 

Other publications of authors with the same name

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm., , , and . VLSI Signal Processing, 46 (1): 35-53 (2007)Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping., , , , , , and . IPDPS, page 190. IEEE Computer Society, (2003)Implementation of (Normalised) RLS Lattice on Virtex., , , , , , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 91-100. Springer, (2001)Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm., , , and . IES, page 1-10. IEEE, (2006)Heterogeneous Platform for Stream Based Applications on FPGAs., , and . FPL, page 401-404. IEEE Computer Society, (2011)FPGA Implementation of the Adpaptive Lattice Filter., , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 1095-1098. Springer, (2003)Using Reconfigurable HW for High Dimensional CAF Computation., , and . FPL, page 1-4. IEEE, (2006)Blind image deconvolution algorithm on NVIDIA CUDA platform., , and . DDECS, page 125-126. IEEE Computer Society, (2010)Architecture design for FPGA implementation of finite interval CMA., , and . EUSIPCO, page 2039-2042. IEEE, (2004)Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA., and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1149-1151. Springer, (2004)