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Novel design of driver and ESD transistors with significantly reduced silicon area.

, , , , and . Microelectron. Reliab., 42 (1): 3-13 (2002)

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High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation., , , , , and . Microelectron. Reliab., 43 (7): 993-1000 (2003)Novel design of driver and ESD transistors with significantly reduced silicon area., , , , and . Microelectron. Reliab., 42 (1): 3-13 (2002)Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies., , , , , , and . CICC, page 251-254. IEEE, (2004)ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies., , , , , , , , and . ISCAS (2), page 1194-1197. IEEE, (2005)Editorial.. Microelectron. Reliab., 41 (3): 333 (2001)ESD protection solutions for high voltage technologies., , , , , and . Microelectron. Reliab., 46 (5-6): 677-688 (2006)Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling., , , , , , , , , and . Microelectron. Reliab., 43 (9-11): 1537-1543 (2003)Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologies., and . Microelectron. Reliab., 41 (11): 1739-1749 (2001)