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Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs.

, , and . J. Supercomput., 35 (2): 185-199 (2006)

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Novel Hardware Implementation of the Cipher Message Authentication Code., , , , and . J. Comput. Networks Commun., (2008)A Novel Data-Path for Accelerating DSP Kernels., , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 363-372. Springer, (2004)Mapping DSP applications on processor/coarse-grain reconfigurable array architectures., , and . ISCAS, IEEE, (2006)Resource constrained modulo scheduling for coarse-grained reconfigurable arrays., , and . ISCAS, IEEE, (2006)Partitioning Methodology for Heterogeneous Reconfigurable Functional Units., , and . J. Supercomput., 38 (1): 17-34 (2006)A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels., , , and . Journal of Circuits, Systems, and Computers, 14 (4): 877-893 (2005)Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware., , and . IPDPS, IEEE, (2006)Speedups in embedded systems with a high-performance coprocessor datapath., , , and . ACM Trans. Design Autom. Electr. Syst., 12 (3): 35:1-35:22 (2007)High-speed hardware implementations of the KASUMI block cipher., , and . ISCAS (2), page 549-552. IEEE, (2004)A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000., , , and . Integr., 39 (1): 1-11 (2005)