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Understanding Power Efficiency of TCP/IP Packet Processing over 10GbE.

, , , , and . Hot Interconnects, page 32-39. IEEE Computer Society, (2010)

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Shuffling: a framework for lock contention aware thread scheduling for multicore multiprocessor systems., , and . PACT, page 289-300. ACM, (2014)Extending Multistage Interconnection Networks for Multitasking., and . ICPP (1), page 151-158. CRC Press, (1992)Reliability Simulation of Multiprocessor Systems., and . ICPP, page 591-598. IEEE Computer Society Press, (1985)Design and Performance of Generalized Interconnection Networks., and . IEEE Trans. Computers, 32 (12): 1081-1090 (1983)Performance Evaluation of a Dataflow Architecture., and . IEEE Trans. Computers, 39 (5): 615-627 (1990)Bandwidth Availability of Multiple-Bus Multiprocessors., and . IEEE Trans. Computers, 34 (10): 918-926 (1985)Fair Scheduling in Internet Routers., and . IEEE Trans. Computers, 51 (6): 686-701 (2002)A Network Processor-Based, Content-Aware Switch., , , and . IEEE Micro, 26 (3): 72-84 (2006)A new IP lookup cache for high performance IP routers., , and . DAC, page 338-343. ACM, (2010)Evaluating Virtual Channels for Cache-Coherent Shared-Memory Multiprocessors., and . International Conference on Supercomputing, page 253-260. ACM, (1996)