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Accurate and Efficient Macromodel of Submicron Digital Standard Cells.

, , and . DAC, page 633-637. ACM Press, (1997)

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DFM rules!, , , , , , , and . DAC, page 168-169. ACM, (2005)Yield-aware placement optimization., , , , , and . DATE, page 1232-1237. EDA Consortium, San Jose, CA, USA, (2007)Automatic characterization and modeling of power consumption in static RAMs., , and . ISLPED, page 112-114. ACM, (1998)Impact Analysis of Process Variability on Clock Skew., , , , , and . ISQED, page 129-132. IEEE Computer Society, (2002)Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs., , and . ASP-DAC, page 45-50. IEEE, (1998)Analog IP Testing: Diagnosis and Optimization., , , , , , and . DATE, page 192-196. IEEE Computer Society, (2002)Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning., , and . CICC, page 31-34. IEEE, (1999)An effective DFM strategy requires accurate process and IP pre-characterization., , , , and . DAC, page 760-761. ACM, (2005)High Yield Standard Cell Libraries: Optimization and Modeling., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 129-137. Springer, (2004)Accurate and Efficient Macromodel of Submicron Digital Standard Cells., , and . DAC, page 633-637. ACM Press, (1997)