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A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution.

, , and . SIGARCH Comput. Archit. News, 43 (4): 40-45 (2015)

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Reconfigurable design with clock gating., , , and . ICSAMOS, page 187-194. IEEE, (2008)Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity., , , , and . FPT, page 162-170. IEEE, (2019)MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration., , , , , and . FPL, page 248-252. IEEE, (2023)Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices., , , and . ARC, volume 13569 of Lecture Notes in Computer Science, page 118-133. Springer, (2022)Performance Estimation for Exascale Reconfigurable Dataflow Platforms., , , , , and . FPT, page 314-317. IEEE, (2018)Specifying Compiler Strategies for FPGA-based Systems., , , , , , and . FCCM, page 192-199. IEEE Computer Society, (2012)Relation-oriented resource allocation for multi-accelerator systems., , , , , , , , and . ASAP, page 243-244. IEEE Computer Society, (2016)Optimising and adapting high-level hardware designs., and . FPT, page 150-157. IEEE, (2002)HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms., , , , , , , , , and 1 other author(s). IEEE Micro, 30 (5): 88-97 (2010)Scheduling Hardware-Accelerated Cloud Functions., , and . J. Signal Process. Syst., 93 (12): 1419-1431 (2021)