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Disambiguation of "Li, Dengquan"

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A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS.

, , , , and . Microelectron. J., (2018)

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Li Li

Li Li

Li Li

Li Li

Li Li

 

Other publications of authors with the same name

A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application., , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (4): 650-654 (2020)A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (9): 3557-3566 (September 2023)A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (10): 1558-1562 (2022)A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS., , and . Microelectron. J., (2022)A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation., , , and . APCCAS, page 53-56. IEEE, (2018)A TD-ADC for IR-UWB Radars With Equivalent Sampling Technology and 8-GS/s Effective Sampling Rate., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (3): 888-892 (2021)A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm., , , , and . IEEE Trans. Instrum. Meas., (2024)A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (11): 1524-1528 (2018)A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS., , , , and . J. Circuits Syst. Comput., 30 (8): 2150143:1-2150143:19 (2021)A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration., , , , , and . CICC, page 1-4. IEEE, (2019)