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Disambiguation of "Nambiar, Vishnu P."

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Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function.

, , , and . Neurocomputing, (2014)

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Raghu Nambiar

Sandeep Nambiar

Smitha Vishnu

Vishnu Kotrajaras

Vishnu Bendre

 

Other publications of authors with the same name

Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (9): 3148-3152 (2021)A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (12): 5081-5094 (2021)Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing., , , , and . SoCC, page 27-32. IEEE, (2019)Accelerating the AES encryption function in OpenSSL for embedded systems., , and . Int. J. Inf. Commun. Technol., 2 (1/2): 83-93 (2009)Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm., , , and . ISCAS, page 1-5. IEEE, (2019)Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers., , , , and . SoCC, page 242-247. IEEE, (2019)A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1662-1666 (2022)A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS., , , , , , and . ISCAS, page 2433-2437. IEEE, (2022)A real-time near infrared image acquisition system based on image quality assessment., , , and . J. Real-Time Image Processing, 13 (1): 103-120 (2017)Co-simulation methodology for improved design and verification of hardware neural networks., , and . IECON, page 2226-2231. IEEE, (2013)