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High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND., , , , and . ICASSP, page 8288-8292. IEEE, (2021)Demo: Universal Soft-Detection Decoder with Ultra-Low Energy Consumption Using ORBGRAND., , , , , , , , and . WoWMoM, page 337-339. IEEE, (2023)Power-delay analysis of an ABACUS parallel integer multiplier VLSI implementation., and . ICEAC, page 1-4. IEEE, (2015)An integrated approach to system-level CPU and memory energy efficiency on computing systems., , and . ICEAC, page 1-6. IEEE, (2012)Reduced-memory high-throughput fast-SSC polar code decoder architecture., , and . SiPS, page 1-6. IEEE, (2017)Improved Bit-Flipping Algorithm for Successive Cancellation Decoding of Polar Codes., , and . IEEE Trans. Commun., 67 (1): 61-72 (2019)Modeling and Simulation for the Operative Service Delivery Planning in the Context of Product-Service Systems., , , and . WSC, page 1936-1947. IEEE, (2023)A General Security Approach for Soft-information Decoding against Smart Bursty Jammers., , , , , and . GLOBECOM (Workshops), page 245-251. IEEE, (2022)A Novel Offset and 1/f Noise Compensated Single-Slope ADC with Reduced Hardware Effort., , and . NEWCAS, page 1-4. IEEE, (2019)Improved successive cancellation flip decoding of polar codes based on error distribution., , and . WCNC Workshops, page 19-24. IEEE, (2018)