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Disambiguation of "Rodrigues, Arun"

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Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation.

, , , , , , , , , and . J. Parallel Distributed Comput., (2017)

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Umeswaran Arunagirinathan

Pattra Arunlakshana

Vinayagam Arunachalam

Arunee Hematulin

Manonmani Arunachalam

 

Other publications of authors with the same name

Scientific applications vs. SPEC-FP: a comparison of program behavior., , , and . ICS, page 66-74. ACM, (2006)The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems., , and . Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 85-103. Springer, (2000)A Hardware Acceleration Unit for MPI Queue Processing., , , , and . IPDPS, IEEE Computer Society, (2005)Achieving Exascale Computing through Hardware/Software Co-design., , , and . EuroMPI, volume 6960 of Lecture Notes in Computer Science, page 5-7. Springer, (2011)Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory., , , and . ISVLSI, page 19-28. IEEE Computer Society, (2003)Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems., , , , , , , , , and 1 other author(s). MEMSYS, page 62-73. ACM, (2016)On the Path to Exascale., , , , , , , , , and 3 other author(s). Int. J. Distributed Syst. Technol., 1 (2): 1-22 (2010)SST: A Scalable Parallel Framework for Architecture-Level Performance, Power, Area and Thermal Simulation., , , , and . Comput. J., 55 (2): 181-191 (2012)Fine-Grained Message Pipelining for Improved MPI Performance., , , and . CLUSTER, IEEE Computer Society, (2006)Implications of a PIM Architectural Model for MPI., , , , , and . CLUSTER, page 259-. IEEE Computer Society, (2003)