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Digitally-assisted analog circuits for a 10 Gbps, 395 fJ/b optical receiver in 40 nm CMOS., , , , , , , , , and 2 other author(s). A-SSCC, page 29-32. IEEE, (2011)A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process., , , , and . IEEE J. Solid State Circuits, 47 (6): 1309-1322 (2012)A fully-integrated optical duobinary transceiver in a 130nm SOI CMOS technology., , , , , and . CICC, page 1-4. IEEE, (2011)Alignment and integration of a hybrid, external-cavity InP-SOI laser., , , , , , , , , and 2 other author(s). OFC, page 1-3. IEEE, (2016)Wavelength locked high-speed microring modulator using an integrated balanced homodyne CMOS control circuit., , , , , , , , , and 4 other author(s). OFC, page 1-3. IEEE, (2016)Optical Interconnect for High-End Computer Systems., , , , , , , , , and 1 other author(s). IEEE Des. Test Comput., 27 (4): 10-19 (2010)10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 47 (9): 2049-2067 (2012)Computer Systems Based on Silicon Photonic Interconnects., , , , , , , , and . Proc. IEEE, 97 (7): 1337-1361 (2009)Energy-Efficient Error Control for Tightly Coupled Systems Using Silicon Photonic Interconnects., , , , , , , , and . JOCN, 3 (8): A21-A31 (2011)Silicon-photonic network architectures for scalable, power-efficient multi-chip systems., , , , , and . ISCA, page 117-128. ACM, (2010)