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Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems., , и . DATE, стр. 1-6. European Design and Automation Association, (2014)BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC., , , , и . ICCD, стр. 78-85. IEEE, (2023)PetaOps/W edge-AI $\mu$ Processors: Myth or reality?, , , , , , , , , и 18 other автор(ы). DATE, стр. 1-6. IEEE, (2023)The Hardware Foundation of 6G: The NEW-6G Approach., , , , , , , , , и 1 other автор(ы). EuCNC, стр. 423-428. IEEE, (2022)Hardware-aware training of models with synaptic delays for digital event-driven neuromorphic processors., , , , , , , , и . CoRR, (2024)Run-time Non-uniform Quantization for Dynamic Neural Networks in Wireless Communication., , и . ASPDAC, стр. 915-920. IEEE, (2024)Architecture and optimal configuration of a real-time multi-channel memory controller., , и . DATE, стр. 1307-1312. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Digital Predistortion with Compressed Observations for Cloud-Based Learning., , , , , и . SiPS, стр. 40-45. IEEE, (2021)Towards ASIP Architecture-Driven Algorithm Development., , и . IESS, том 576 из IFIP Advances in Information and Communication Technology, стр. 91-100. Springer, (2019)Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (3): 1210-1220 (2022)