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A New Optimized Queueing Model with Compensation and Buffer.

, , , , , and . BIBM, page 1452-1456. IEEE Computer Society, (2018)

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Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (8): 3297-3307 (2022)A New Optimized Queueing Model with Compensation and Buffer., , , , , and . BIBM, page 1452-1456. IEEE Computer Society, (2018)COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (4): 596-600 (April 2023)Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform., , , and . FCCM, page 114-120. IEEE, (2023)HPMA-Saber: High-Performance Polynomial Multiplication Accelerator for KEM Saber., , , and . ICCD, page 525-528. IEEE, (2022)Systolic Acceleration of Polynomial Multiplication for KEM Saber and Binary Ring-LWE Post-Quantum Cryptography., , and . HOST, page 157-160. IEEE, (2022)Efficient Hardware RNS Decomposition for Post-Quantum Signature Scheme Falcon., , , and . ACSSC, page 19-26. IEEE, (2023)AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC., , , and . ICFPT, page 6. IEEE, (2023)Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform., , and . FPGA, page 156. ACM, (2022)Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography., , , and . CODES+ISSS, page 5-6. IEEE, (2022)