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Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine.

, , and . EUROMICRO, page 1326-1334. IEEE Computer Society, (1999)

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Bi-Directional Synthesis of 4-Bit Reversible Circuits., , , and . Comput. J., 51 (2): 207-215 (2008)Minimization of GRM Forms with a Genetic Algorithm, and . Genetic Programming 1997: Proceedings of the Second Annual Conference, page 362. Stanford University, CA, USA, Morgan Kaufmann, (13-16 July 1997)A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays., , , and . DAC, page 321-326. ACM Press, (1994)Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping., and . EURO-DAC, page 8-13. IEEE Computer Society, (1994)A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits., , and . IEEE Trans. Computers, 49 (3): 267-276 (2000)Quantum ternary parallel adder/subtractor with partially-look-ahead carry., and . J. Syst. Archit., 53 (7): 453-464 (2007)Fault Models for Quantum Mechanical Switching Networks., , and . J. Electron. Test., 26 (5): 499-511 (2010)A Group Algebraic Approach to NPN Classification of Boolean Functions., , , , , and . Theory Comput. Syst., 63 (6): 1278-1297 (2019)Universality of Hybrid Quantum Gates and Synthesis Without Ancilla Qudits., , , and . CIAA, volume 4094 of Lecture Notes in Computer Science, page 279-280. Springer, (2006)Synthesis of memristive circuits based on stateful IMPLY gates using an evolutionary algorithm with a correction function., , and . NANOARCH, page 97-102. ACM, (2016)