( en | de | ru )

 

Disambiguation of "Abdelsalam, Mohamed"

Author of the publication

copydeleteadd this publication to your clipboard
System Verilog Assertions Synthesis Based Compiler.

, , , , , and . MTV, page 65-70. IEEE Computer Society, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Abdelsalam Mohamed Ismail

Hussein Mohamed Abdelsalam Abdelfatah

Mohamed ElFaisal Abdelsalam El Refaie

Ashraf Abdelsalam

Abdelsalam Heder

 

Other publications of authors with the same name

A Reusable UVM-SystemC Verification Environment for Simulation, Hardware Emulation, and FPGA Prototyping: Case Studies., , , and . ICM, page 38-41. IEEE, (2022)RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC., , , , , , , and . PDP, page 617-621. IEEE Computer Society, (2018)A Configurable RISC-V for NoC-Based MPSoCs: A Framework for Hardware Emulation., , , , and . NoCArc@MICRO, page 1-6. IEEE Computer Society, (2018)A novel approach for functional verification of memory protocol standard., , , , , , and . IDT, page 1-3. IEEE, (2013)Using Path Planning Algorithms and Digital Twin Simulators to Collect Synthetic Training Dataset for Drone Autonomous Navigation., , , , , , , , and . ICECS, page 1-6. IEEE, (2021)A Proposed Model for Improving the Reliability of Online Exam Results Using Blockchain., , and . IEEE Access, (2024)NVMe Solid State Drive verification solution using HW Emulation and Virtual Device Technologies.. IDT, page 47-52. IEEE, (2016)Emulation and verification framework for MPSoC based on NoC and RISC-V., , , , and . Des. Autom. Embed. Syst., 26 (3): 133-159 (December 2022)IPingPong: A Real-time Performance Analyzer System for Table Tennis Stroke's Movements., , , , , , and . FNC/MobiSPC, volume 175 of Procedia Computer Science, page 80-87. Elsevier, (2020)A novel approach for assertion based verification of DDR memory protocols., , , and . FDL, page 1-4. IEEE, (2013)