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Adapting instruction level parallelism for optimizing leakage in VLIW architectures.

, , , and . LCTES, page 275-283. ACM, (2003)

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Compiler-guided leakage optimization for banked scratch-pad memories., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1136-1146 (2005)A Matrix-Based Approach to Global Locality Optimization., , , and . J. Parallel Distributed Comput., 58 (2): 190-235 (1999)Minimizing Data and Synchronization Costs in One-Way Communication., , , , and . IEEE Trans. Parallel Distributed Syst., 11 (12): 1232-1251 (2000)Changing Interaction of Compiler and Architecture., , , , , , , , , and 1 other author(s). Computer, 30 (12): 51-58 (1997)Compiler-Directed Collective-I/O.. IEEE Trans. Parallel Distributed Syst., 12 (12): 1318-1331 (2001)Adaptive prefetching for shared cache based chip multiprocessors., , and . DATE, page 773-778. IEEE, (2009)Performance aware secure code partitioning., , and . DATE, page 1122-1127. EDA Consortium, San Jose, CA, USA, (2007)Memory bank aware dynamic loop scheduling., , , and . DATE, page 1671-1676. EDA Consortium, San Jose, CA, USA, (2007)FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads., , and . HPCA, page 426-439. IEEE, (2019)Using data replication to reduce communication energy on chip multiprocessors., , , and . ASP-DAC, page 769-772. ACM Press, (2005)