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Disambiguation of "Goutis, Costas E."

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Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays.

, , and . SoC, page 1-4. IEEE, (2008)

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Peter Costas

Costas Averkiou

Costas Higoumenakis

Ilse Costas

Costas Panayotakis

 

Other publications of authors with the same name

High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach., , , , , and . SECRYPT, page 126-135. SciTePress, (2012)Speedups in embedded systems with a high-performance coprocessor datapath., , , and . ACM Trans. Design Autom. Electr. Syst., 12 (3): 35:1-35:22 (2007)Spectra using data distribution and covariance modelling., , and . ICASSP, page 642-645. IEEE, (1984)On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs., , , and . Integr., 47 (4): 387-407 (2014)A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices., , , and . J. Signal Process. Syst., 77 (3): 241-255 (2014)An ANNs-based system for the diagnosis and treatment of diseases., , and . Neural Processing Letters, 2 (1): 22-26 (1995)Implementation of HSSec: a high-speed cryptographic co-processor., , , and . ETFA, page 625-631. IEEE, (2007)Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture., , and . J. Supercomput., 40 (2): 127-157 (2007)Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse., , , , , , and . IET Comput. Digit. Tech., 3 (1): 109-123 (2009)A low power fault secure timer implementation based on the Gray encoding scheme., , , and . ICECS, page 537-540. IEEE, (2002)