( en | de | ru )

 

Disambiguation of "Shen, Meng-Hung"

Author of the publication

copydeleteadd this publication to your clipboard
A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops.

, , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (5): 409-413 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hung-Meng Liang

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)

Matthias Meng

 

Other publications of authors with the same name

A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2-10.1 GHz PLL., and . IEEE Trans. Very Large Scale Integr. Syst., 23 (1): 184-188 (2015)A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (11): 825-829 (2014)Optimization processing unit (OPU) applied to integrated circuit design and manufacturing., , , , , , and . CASE, page 1008-1015. IEEE, (2013)A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques., , , , and . VLSI-DAT, page 1-4. IEEE, (2012)Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC., , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (5): 369-373 (2010)A Low Cost Calibrated DAC for High-Resolution Video Display System., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (9): 1743-1747 (2012)A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics., , , , , , , and . IEEE J. Solid State Circuits, 50 (11): 2533-2548 (2015)A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection., , , and . A-SSCC, page 357-360. IEEE, (2011)A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS., , , , and . ISCAS, page 981-984. IEEE, (2011)A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops., , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (5): 409-413 (2008)