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Disambiguation of "Ohtsuki, Tatsuo"

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A thread partitioning algorithm in low power high-level synthesis.

, , , and . ASP-DAC, page 74-79. IEEE Computer Society, (2004)

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Takashi Ohtsuki

Tatsuo Oguro

Tatsuo Oguro

Tatsuo Oguro

Tatsuo Oguro

 

Other publications of authors with the same name

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n)., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (9): 2304-2317 (2009)A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 3218-3224 (2003)One-dimensional logic gate assignment and interval graphs., , , , and . COMPSAC, page 101-106. IEEE, (1979)Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n)., , , , , , , and . ASP-DAC, page 697-702. IEEE, (2008)State-dependent changeable scan architecture against scan-based side channel attacks., , , , , and . ISCAS, page 1867-1870. IEEE, (2010)The two disjoint path problem and wire routing design.. Graph Theory and Algorithms, volume 108 of Lecture Notes in Computer Science, page 207-216. Springer, (1980)A Simultaneous Placement and Global Routing Algorithm for FPGAs., , and . ISCAS, page 483-486. IEEE, (1994)High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (4): 827-834 (2002)An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays., , , and . ASP-DAC, page 519-526. IEEE, (1998)Area/delay estimation for digital signal processor cores., , , , and . ASP-DAC, page 156-161. ACM, (2001)