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SoCCom: Automated Synthesis of System-on-Chip Architectures.

, , , и . IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 449-462 (2022)

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Sandip Agarwala

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Modeling and verification of industrial flash memories., , , и . ISQED, стр. 705-712. IEEE, (2010)Mechanized Information Flow Analysis through Inductive Assertions., , , и . FMCAD, стр. 1-4. IEEE, (2008)Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis., , , и . ACL2, том 152 из EPTCS, стр. 111-128. (2014)Handling design and implementation optimizations in equivalence checking for behavioral synthesis., , , и . DAC, стр. 117:1-117:6. ACM, (2013)Proof Styles in Operational Semantics., и . FMCAD, том 3312 из Lecture Notes in Computer Science, стр. 67-81. Springer, (2004)Security of Multi-Agent Cyber-Physical Systems: A Survey., и . IEEE Access, (2022)Guarding Deep Learning Systems With Boosted Evasion Attack Detection and Model Update., , , и . IEEE Internet Things J., 11 (6): 9382-9391 (марта 2024)SoCCom: Automated Synthesis of System-on-Chip Architectures., , , и . IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 449-462 (2022)Internet-of-Things Security and Vulnerabilities: Taxonomy, Challenges, and Practice., , , , , , и . J. Hardw. Syst. Secur., 2 (2): 97-110 (2018)SeVNoC: Security Validation of System-on-Chip Designs With NoC Fabrics., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 672-682 (февраля 2023)