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A low power VLSI architecture for multistage interval-based motion estimation (MIME) algorithm.

, , , , and . DCV, page 159-166. IEEE, (2002)

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Multi-Path Search Algorithm for Block-Based Motion Estimation., and . ICIP, page 2373-2376. IEEE, (2006)High-speed Motion Estimation Architecture for Real-time Video Transmission., , and . Comput. J., 55 (1): 35-46 (2012)Novel Design Methodology for High-Performance XOR-XNOR Circuit Design., , and . SBCCI, page 71-. IEEE Computer Society, (2003)Memory accesses reduction for MIME algorithm., , , , and . ICME, page 805-808. IEEE Computer Society, (2003)An Efficient Data Reuse Motion Estimation Engine., , , , and . SiPS, page 383-386. IEEE, (2006)Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style., , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (12): 1309-1321 (2006)Energy Efficient and Noise-Tolerant XOR-XNOR Circuit Design., , and . VLSI, page 125-130. CSREA Press, (2003)A New Efficient Block-Matching Algorithm for Motion Estimation., , , and . VLSI Signal Processing, 42 (1): 21-33 (2006)Noise tolerant low voltage XOR-XNOR for fast arithmetic., , and . ACM Great Lakes Symposium on VLSI, page 285-288. ACM, (2003)A low power VLSI architecture for multistage interval-based motion estimation (MIME) algorithm., , , , and . DCV, page 159-166. IEEE, (2002)