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ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3015-3028 (2015)The Mesochronous Dual-Clock FIFO Buffer., , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (1): 302-306 (2020)High-Speed Parallel-Prefix VLSI Ling Adders., and . IEEE Trans. Computers, 54 (2): 225-231 (2005)Virtual-scan: a novel approach for software-based self-testing of microprocessors., , and . ISCAS (5), page 237-240. IEEE, (2003)Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching., , , and . Integr., (2021)A Dual-Clock Multiple-Queue Shared Buffer., , , and . IEEE Trans. Computers, 66 (10): 1809-1815 (2017)ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing., , , and . IEEE Trans. Computers, 65 (10): 3136-3147 (2016)Reusing Softmax Hardware Unit for GELU Computation in Transformers., , and . CoRR, (2024)IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications., , , , and . CoRR, (2023)LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride., , and . ISVLSI, page 200-205. IEEE, (2022)