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Disambiguation of "Ghosh, Sudip"

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Implementation of Area Efficient Adders for Inexact Computing.

, , and . ISDCS, page 1-4. IEEE, (2023)

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Sudip Roy

Sudip Kundu

Michael Ghosh

Subhajit Ghosh

Arabinda Ghosh

 

Other publications of authors with the same name

FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time., , , and . J. Real-Time Image Processing, 14 (1): 193-221 (2018)Advancements on reliability-aware analog circuit design., , , , , , , , , and . ESSCIRC, page 46-52. IEEE, (2012)Thermal aging model of InP/InGaAs/InP DHBT., , , , , and . Microelectron. Reliab., 50 (9-11): 1554-1558 (2010)A New Blind Invisible and Semi-Fragile Colour Image Watermarking Scheme in Spatial Domain., , , and . ISDCS, page 1-6. IEEE, (2020)Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA., , , and . ISED, page 68-72. IEEE Computer Society, (2014)Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach., , , , , , and . Circuits Syst. Signal Process., 37 (12): 5690 (2018)Implementation of Area Efficient Adders for Inexact Computing., , and . ISDCS, page 1-4. IEEE, (2023)B rainMN et: a unified neural network architecture for brain image classification., , and . Netw. Model. Anal. Health Informatics Bioinform., 13 (1): 11 (December 2024)Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra., , , , , , , and . IAIT, page 23:1-23:6. ACM, (2023)Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA., , , , and . ICIT, page 123-128. IEEE, (2014)