( en | de | ru )

 

Disambiguation of "Raghunathan, Anand"

Author of the publication

copydeleteadd this publication to your clipboard
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage.

, , , and . ACM J. Emerg. Technol. Comput. Syst., 12 (1): 4:1-4:27 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Davinder Kumar Anand

Raghunathan Ramakrishnan

Devanathan Raghunathan

Amar Frank Anand

Madhankumar Anandhakrishnan

 

Other publications of authors with the same name

Software Architectural Transformations, , and . (2004)Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips., , , and . DAC, page 513-518. ACM, (2000)Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (3): 296-308 (2007)Variation-Aware System-Level Power Analysis., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1173-1184 (2010)High-level macro-modeling and estimation techniques for switching activity and power consumption., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (4): 538-557 (2003)Emulation-Based Analysis of System-on-Chip Performance Under Variations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3401-3414 (2016)Input Compression with Positional Consistency for Efficient Training and Inference of Transformer Neural Networks., and . CoRR, (2023)System-on-Chip Power Management Considering Leakage Power Variations., , , and . DAC, page 877-882. IEEE, (2007)Hardware Accelerated Power Estimation, , and . CoRR, (2007)STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks., , , and . CoRR, (2014)