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CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (7): 2548-2561 (2016)

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Affine transformations for communication and reconfiguration optimization of loops on CGRAs., , , and . ISCAS, page 2541-2544. IEEE, (2013)Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , and . ISCAS, page 1-4. IEEE, (2017)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , and . DAC, page 64:1-64:6. ACM, (2016)Polyhedral model based mapping optimization of loop nests for CGRAs., , , and . DAC, page 19:1-19:8. ACM, (2013)Multipath Energy Efficient Routing in Mobile Ad Hoc Network., and . ICN (2), volume 3421 of Lecture Notes in Computer Science, page 226-233. Springer, (2005)Energy-aware loops mapping on multi-vdd CGRAs without performance degradation., , , and . ASP-DAC, page 312-317. IEEE, (2017)AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs., , , , , , , , , and . NVMSA, page 1-6. IEEE, (2017)PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement., , , , , , and . ICASSP, page 6234-6238. IEEE, (2020)A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration., , , , and . IEEE Comput. Archit. Lett., 15 (2): 69-72 (2016)A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction., , , , , , , and . IEEE J. Solid State Circuits, 57 (5): 1542-1557 (2022)