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A 390Mb/s 3.57mm2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS., , , and . ISSCC, page 274-275. IEEE, (2010)A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End., , , and . ISSCC, page 260-601. IEEE, (2007)Implementation Trade-Offs of Soft-Input Soft-Output MAP Decoders for Convolutional Codes., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (11): 2774-2783 (2012)Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE., , , and . IEEE J. Solid State Circuits, 46 (1): 8-17 (2011)A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS., , , and . ISSCC, page 264-265. IEEE, (2008)Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE., and . VLSI-SoC (Selected Papers), volume 373 of IFIP Advances in Information and Communication Technology, page 100-127. Springer, (2010)A 4.5mW digital baseband receiver for level-A evolved EDGE., , and . ISSCC, page 276-277. IEEE, (2010)A 1.9 GS/s 4-bit sub-Nyquist flash ADC for 3.8 GHz compressive spectrum sensing in 28 nm CMOS., , , , , and . MWSCAS, page 101-104. IEEE, (2014)Turbo decoder design for high code rates., , and . VLSI-SoC, page 71-75. IEEE, (2012)Low-complexity frequency synchronization for GSM systems: Algorithms and implementation., , , , and . ICUMT, page 168-173. IEEE, (2012)