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Disambiguation of "Roy, Sujoy Sinha"

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Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 810-818 (2015)

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Prashant Sinha

Intermediate states in bivalent ion induced shrinking of polyacrylate coils on surfaces and in solution. TU Dresden, (2009)

Vineet Sinha

Jyoti Sinha

Raunak Sinha

Rileen Sinha

 

Other publications of authors with the same name

KaLi: A Crystal for Post-Quantum Security Using Kyber and Dilithium., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (2): 747-758 (February 2023)Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs., , and . CHES, volume 7428 of Lecture Notes in Computer Science, page 494-511. Springer, (2012)FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data., , , , and . HPCA, page 387-398. IEEE, (2019)A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange., , , , , , and . IACR Cryptol. ePrint Arch., (2021)On Exploiting Message Leakage in (few) NIST PQC Candidates for Practical Message Recovery and Key Recovery Attacks., , , and . IACR Cryptol. ePrint Arch., (2020)Towards a constant-time implementation of isogeny-based signature, SQISign., , , and . IACR Cryptol. ePrint Arch., (2023)Exploring RNS for Isogeny-based Cryptography., , and . IACR Cryptol. ePrint Arch., (2022)Parallel Hardware for Isogeny-based VDF: Attacker's Perspective., , , and . IACR Cryptol. ePrint Arch., (2023)High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (1): 157-166 (2015)Compact and Side Channel Secure Discrete Gaussian Sampling., , , and . IACR Cryptology ePrint Archive, (2014)