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Hardware implementation of KLMS algorithm using FPGA., , , , and . IJCNN, page 2276-2281. IEEE, (2014)HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems., , , , , and . HPCA, page 582-595. IEEE, (2020)Fault-tolerant Routing for On-chip Network Without Using Virtual Channels., , , and . DAC, page 102:1-102:6. ACM, (2014)A reconfigurable parallel FPGA accelerator for the kernel affine projection algorithm., , , , and . DSP, page 906-910. IEEE, (2015)A Deadlock-Free and Connectivity-Guaranteed Methodology for Achieving Fault-Tolerance in On-Chip Networks., , , , and . IEEE Trans. Computers, 65 (2): 353-366 (2016)CHOPIN: Scalable Graphics Rendering in Multi-GPU Systems via Parallel Image Composition., and . HPCA, page 709-722. IEEE, (2021)Dynamic Partial Order Reductions for Spinloops., , and . FMCAD, page 163-172. IEEE, (2021)A real-time permutation entropy computation for EEG signals., , , , and . ASP-DAC, page 20-21. IEEE, (2015)A 128-way FPGA platform for the acceleration of KLMS algorithm., , , , and . ASP-DAC, page 18-19. IEEE, (2015)Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training., , , , , and . MICRO, page 711-724. IEEE, (2020)