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A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2549-2560 (2014)

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A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer., , , , , and . ApplePies, volume 627 of Lecture Notes in Electrical Engineering, page 505-511. Springer, (2019)Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops., , and . Microelectron. Reliab., 55 (12): 2614-2626 (2015)Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder., , , , and . ISC Workshops, volume 11203 of Lecture Notes in Computer Science, page 545-553. Springer, (2018)A Simple Microwave Imaging System for Food Product Inspection through a Symmetry-Based Microwave Imaging Approach., , , , , , and . Sensors, 24 (1): 99 (2024)Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration., , , , and . PRIME, page 237-240. IEEE, (2022)Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment., , , , , , , , and . DFT, page 1-6. IEEE, (2020)Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores., , , , , and . CoRR, (2020)The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes., , , , and . ApplePies, volume 512 of Lecture Notes in Electrical Engineering, page 89-97. Springer, (2017)Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores., , , , , and . IEEE Micro, 41 (2): 64-71 (2021)Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators., , , , , , and . ApplePies, volume 1036 of Lecture Notes in Electrical Engineering, page 149-154. Springer, (2022)