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45pW ESD clamp circuit for ultra-low power applications., , , , , and . CICC, page 1-4. IEEE, (2013)A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC., , , and . Journal of Circuits, Systems, and Computers, 25 (12): 1650155:1-1650155:16 (2016)A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration., , , , , and . ISSCC, page 112-113. IEEE, (2008)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (10): 687-691 (2011)A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (2): 91-95 (2013)A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (3): 142-146 (2013)5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (5): 269-273 (2011)A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement., , , , , and . IEEE J. Solid State Circuits, 51 (8): 1902-1914 (2016)A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation., , , and . IEEE J. Solid State Circuits, 48 (9): 2118-2127 (2013)