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Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications.

, , , and . ACA, volume 908 of Communications in Computer and Information Science, page 95-108. Springer, (2018)

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Efficient custom instructions generation for system-level design., , and . FPT, page 445-448. IEEE, (2010)A Framework to Model Branch Prediction for WCET Analysis, and . (June 2002)Short version of: A Framework to Model Branch Prediction for WCET Analysis, Tulika Mitra, Abhik Roychoudhury, 2nd Workshop on Worst Case Execution Time Analysis (WCET), Austria, June 2002. Also available as NUS Technical Report 11-01. One of Author's homepage: http://www.comp.nus.edu.sg/~abhik/.An efficient framework for dynamic reconfiguration of instruction-set customization., , and . CASES, page 135-144. ACM, (2007)Static analysis for fast and accurate design space exploration of caches., and . CODES+ISSS, page 103-108. ACM, (2008)Integrated instruction cache analysis and locking in multitasking real-time systems., , and . DAC, page 147:1-147:10. ACM, (2013)Exploiting forwarding to improve data bandwidth of instruction-set extensions., , and . DAC, page 43-48. ACM, (2006)Characterizing embedded applications for instruction-set extensible processors., and . DAC, page 723-728. ACM, (2004)Cache modeling in probabilistic execution time analysis., and . DAC, page 319-324. ACM, (2008)Analyzing Loop Paths for Execution Time Estimation., , and . ICDCIT, volume 3816 of Lecture Notes in Computer Science, page 458-469. Springer, (2005)Instruction-set customization for real-time embedded systems., and . DATE, page 1472-1477. EDA Consortium, San Jose, CA, USA, (2007)