Author of the publication

Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique.

, , , , , and . ECCTD, page 356-359. IEEE, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver., and . ISCAS (1), page 528-531. IEEE, (2001)Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier., and . ISCAS, page 1568-1571. IEEE, (1995)Design of a 10-bit CMOS image sensor based on an 8-bit configurable hold-and-go counter., , , and . ESSCIRC, page 393-397. IEEE, (2012)Design of a 7-bit 1GSPS folding-interpolation A/D converter with self-calibration technique., , , , , and . ICECS, page 110-113. IEEE, (2010)A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters., , and . IEEE Trans. Consumer Electronics, 46 (3): 903-906 (2000)Design of a Feature Extracted CMOS Image Sensor with a Novel Integrator and a Configurable ADC., and . ICM, page 237-240. IEEE, (2022)On-CMOS Image Sensor Processing for Lane Detection., , , , and . Sensors, 21 (11): 3713 (2021)Design of a Hybrid Column Segmented CMOS Image Sensor with an Artificial Intelligence Core and a Novel SRAM Readout Logic., , , and . ICEIC, page 1-2. IEEE, (2019)Compute-in-Memory with SAR ADC and 2T1C DRAM for MAC Operations., , , , , , , , and . ICEIC, page 1-3. IEEE, (2024)Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)., , , , and . ICECS, page 1033-1036. IEEE, (1996)