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Disambiguation of "Cazorla, Francisco J."

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RVC-based time-predictable faulty caches for safety-critical systems.

, , , , and . IOLTS, page 25-30. IEEE Computer Society, (2011)

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Francisco Castellanos

Francisco Gaona

Francisco Cardiel

Francisco Garcés

Francisco Carabelli

 

Other publications of authors with the same name

Feasibility of QoS for SMT., , , , , and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 535-540. Springer, (2004)An Analyzable Memory Controller for Hard Real-Time CMPs., , , and . IEEE Embed. Syst. Lett., 1 (4): 86-90 (2009)Enabling SMT for real-time embedded systems., , , , , and . EUSIPCO, page 1341-1344. IEEE, (2004)Kilo-Instruction Processors: Overcoming the Memory Wall., , , , , , and . IEEE Micro, 25 (3): 48-57 (2005)Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments., , , , and . IEEE Micro, 34 (6): 8-19 (2014)Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain., , , , , and . IEEE Micro, 38 (6): 46-55 (2018)Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262., , , , , , and . IEEE Trans. Reliab., 67 (3): 1314-1327 (2018)Uncertainty Management in Dependable and Intelligent Embedded Software., , and . Computer, 56 (3): 114-117 (March 2023)Hardware support for accurate per-task energy metering in multicore systems., , , , , and . ACM Trans. Archit. Code Optim., 10 (4): 34:1-34:27 (2013)Fair CPU time accounting in CMP+SMT processors., , , and . ACM Trans. Archit. Code Optim., 9 (4): 50:1-50:25 (2013)