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Reliability And Performance Challenges Of Ultra-Low Voltage Caches: A Trade-Off Analysis., and . IOLTS, page 265-268. IEEE, (2018)Reliability aspects of binary vector-matrix-multiplications using ReRAM devices., , , , , , , , , and . Neuromorph. Comput. Eng., 2 (3): 34001 (2022)Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs., , , , and . VLSI-SoC, page 1-6. IEEE, (2022)RRAM Crossbar-Based Fault-Tolerant Binary Neural Networks (BNNs)., , and . ETS, page 1-2. IEEE, (2022)Special Session: STT-MRAMs: Technology, Design and Test., , , , , and . VTS, page 1-10. IEEE, (2022)Fine-Grained Energy-Constrained Microprocessor Pipeline Design., and . IEEE Trans. Very Large Scale Integr. Syst., 26 (3): 457-469 (2018)Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems., and . ACM Trans. Design Autom. Electr. Syst., 26 (3): 21:1-21:23 (2021)Resilient Energy-Constrained Microprocessor Architectures.. Karlsruhe Institute of Technology, Germany, (2019)A Lightweight Architecture for Real-Time Neuronal-Spike Classification., , , , , , , , and . CoRR, (2023)PetaOps/W edge-AI $\mu$ Processors: Myth or reality?, , , , , , , , , and 18 other author(s). DATE, page 1-6. IEEE, (2023)