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Disambiguation of "Cong, Jason"

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Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs.

, , , , , , , and . IEEE Trans. Computers, 69 (7): 931-943 (2020)

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Ian Jason

Martha Congehl

Irene Congehl

Salvador Congost Zimmermann

Lina Cong

 

Other publications of authors with the same name

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (4): 564-577 (2010)Buffer block planning for interconnect planning and prediction., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 929-937 (2001)Wire width planning for interconnect performance optimization., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (3): 319-329 (2002)Pin assignment with global routing for general cell designs.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (11): 1401-1412 (1991)Power modeling and characteristics of field programmable gate arrays., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1712-1724 (2005)Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (1): 24-39 (1998)Routability-Driven Placement and White Space Allocation., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (5): 858-871 (2007)Acceleration of EM-Based 3D CT Reconstruction Using FPGA., and . IEEE Trans. Biomed. Circuits Syst., 10 (3): 754-767 (2016)A provably good multilayer topological planar routing algorithm in IC layout designs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (1): 70-78 (1993)FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (1): 1-12 (1994)