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Disambiguation of "Audzevich, Yury"

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Packet Loss Minimization in Load-Balancing Switch.

, , , and . ASMTA, volume 6148 of Lecture Notes in Computer Science, page 44-58. Springer, (2010)

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Tatsiana Audzevich

Ruslan Yuryev

Yury Postnikov

Yury Markovskiy

Yury Valdau

 

Other publications of authors with the same name

A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances., , , and . ReConFig, page 1-6. IEEE, (2015)Packet Loss Analysis of Load-Balancing Switch with ON/OFF Input Processes., , , and . EPEW, volume 5652 of Lecture Notes in Computer Science, page 197-211. Springer, (2009)NetFPGA - rapid prototyping of high bandwidth devices in open source., , , , , and . FPL, page 1. IEEE, (2015)Scalable Model for Packet Loss Analysis of Load-Balancing Switches with Identical Input Processes., , , and . ASMTA, volume 5513 of Lecture Notes in Computer Science, page 249-263. Springer, (2009)NetFPGA: Rapid Prototyping of Networking Devices in Open Source., , , , , and . SIGCOMM, page 363-364. ACM, (2015)Power Optimized Transceivers for Future Switched Networks., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (10): 2081-2092 (2014)Analysis of Load-Balanced Switch with Finite Buffers., , , and . GLOBECOM, page 1524-1529. IEEE, (2008)NetFPGA SUME: Toward 100 Gbps as Research Commodity., , , and . IEEE Micro, 34 (5): 32-41 (2014)Packet Loss Minimization in Load-Balancing Switch., , , and . ASMTA, volume 6148 of Lecture Notes in Computer Science, page 44-58. Springer, (2010)Assessment and Open-Issues of the Load-Balanced Switching Architecture., and . FGCN (1), page 54-61. IEEE Computer Society, (2008)