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A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector.

S. Choi, S. Yoo, Y. Lim, and J. Choi. IEEE J. Solid State Circuits, 51 (8): 1878-1889 (2016)

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Andreas Choi

Bongkyung Choi

Youngmi Choi

Jinsub Choi

Carmen Choi

Other publications of authors with the same name

A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs.Y. Lee, M. Kim, T. Seong, and J. Choi. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (3): 635-644 (2015)Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers.T. Seong, J. Kim, and J. Choi. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (3): 781-790 (2015)Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration.T. Seong, Y. Lee, and J. Choi. IEEE Trans. Circuits Syst. II Express Briefs, 61-II (9): 701-705 (2014)A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration.H. Yoon, S. Park, and J. Choi. IEEE J. Solid State Circuits, 54 (6): 1564-1574 (2019)An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique.Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi. IEEE J. Solid State Circuits, 53 (9): 2675-2685 (2018)A 65-nm CMOS 2×2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations.K. Lim, S. Lee, Y. Lee, B. Moon, H. Shin, K. Kang, S. Kim, J. Lee, H. Lee, H. Shim and 13 other author(s). IEEE J. Solid State Circuits, 53 (7): 1960-1976 (2018)A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC.T. Seong, Y. Lee, S. Yoo, and J. Choi. ISSCC, page 396-398. IEEE, (2018)10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector.S. Choi, S. Yoo, and J. Choi. ISSCC, page 194-195. IEEE, (2016)A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation.J. Kim, Y. Jo, H. Park, T. Seong, Y. Lim, and J. Choi. IEEE J. Solid State Circuits, 59 (2): 424-434 (February 2024)A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector.Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi. ESSCIRC, page 210-213. IEEE, (2018)

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Disambiguation of "Choi, Jaehyouk"