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Sensitivity Analysis of Critical Parameters in Board Test., and . IEEE Des. Test Comput., 13 (1): 58-63 (1996)Issues in Optimizing the Test Process - A Telecom Case Study., , and . ITC, page 800-808. IEEE Computer Society, (1996)ASIC Manufacturing Test Cost Prediction at Early Design Stage., , and . ITC, page 356-361. IEEE Computer Society, (1997)Defects, Fault Coverage, Yield and Cost in Board Manufacturing., and . ITC, page 539-547. IEEE Computer Society, (1994)ASIC Yield Estimation at Early Design Cycle., , and . ITC, page 590-594. IEEE Computer Society, (1996)Opens Board Test Coverage: When is 99% Really 40%?, , and . ITC, page 333-339. IEEE Computer Society, (1996)A new methodology for improved tester utilization., , , , , and . ITC, page 916-923. IEEE Computer Society, (2001)Fault Coverage Estimation for Early Stage of VLSI Design., , and . Great Lakes Symposium on VLSI, page 105-108. IEEE Computer Society, (1999)Board Test DFT Model for Computer Products., , and . ITC, page 367-371. IEEE Computer Society, (1992)Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs., and . ITC, page 903-910. IEEE Computer Society, (1994)