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Disambiguation of "Samori, Carlo"

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A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations.

, , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3645-3649 (2022)

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Paolo Samorí

Teresa Carlomagno

Lothar Carlowitz

Horst Carlowitz

Hans Carlowitz

 

Other publications of authors with the same name

A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power., , , , , and . IEEE J. Solid State Circuits, 46 (12): 2745-2758 (2011)A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power., , , and . IEEE J. Solid State Circuits, 47 (12): 2974-2988 (2012)5-GHz in-phase coupled oscillators with 39% tuning range., , , , and . CICC, page 269-272. IEEE, (2004)A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , and . IEEE J. Solid State Circuits, 58 (9): 2466-2477 (September 2023)Phase noise in digital frequency dividers., , , , and . IEEE J. Solid State Circuits, 39 (5): 775-784 (2004)Analysis and design of a 1.8-GHz CMOS LC quadrature VCO., , , and . IEEE J. Solid State Circuits, 37 (12): 1737-1747 (2002)A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power., , , , , and . ISSCC, page 88-90. IEEE, (2011)An efficient method to compute phase-noise in injection-locked frequency dividers., , , and . ISCAS, page 1753-1756. IEEE, (2013)Background adaptive linearization of high-speed digital-to-analog Converters., , , and . ISCAS, page 582-585. IEEE, (2013)Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter., , , , and . CICC, page 133-136. IEEE, (2006)