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Disambiguation of "Theodoridis, George"

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Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion.

, , , and . ISVLSI, page 119-124. IEEE Computer Society, (2015)

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Alexandros Theodoridis

Karolina Theodoridis

Ulrike Theodoridis

Theodoros Theodoridis

Christos Theodoridis

 

Other publications of authors with the same name

On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function., , , , and . SECRYPT, page 270-275. SciTePress, (2012)A novel coarse-grain reconfigurable data-path for accelerating DSP kernels., , , , and . FPGA, page 252. ACM, (2004)Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs., , , , , and . Journal of Circuits, Systems, and Computers, 25 (4): 1650032:1-1650032:26 (2016)A high performance data-path to accelerate DSP kernels., , , , and . ICECS, page 495-498. IEEE, (2004)Power aware data type refinement on the HIPERLAN/2., , , , , and . ICECS, page 216-219. IEEE, (2003)A Novel Constant-Time Fault-Secure Binary Counter., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 742-749. Springer, (2004)A method for partitioning applications in hybrid reconfigurable architectures., , , , and . Des. Autom. Embed. Syst., 10 (1): 27-47 (2005)A high-performance data path for synthesizing DSP kernels., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1154-1162 (2006)Optimising the SHA-512 cryptographic hash function on FPGAs., , , and . IET Comput. Digit. Tech., 8 (2): 70-82 (2014)A Fast and Accurate Method of Power Estimation for Logic Level Networks., , , and . VLSI Design, 12 (2): 205-219 (2001)